There are various methods for manufacturing a device embedded substrate (e.g., see Patent Document 1). In such a method, a bonding layer is formed on a copper foil by means of a dispenser or by a printing method, a device to be embedded is mounted on the bonding layer, and the device is fixed by curing the bonding layer. Then, the device is embedded inside an insulation material by laminating press, and a via which reaches the terminal of the device from the outside is formed by laser processing. Then, this via is plated and turned into a conductive via to establish electrical connection with the terminal.
However, when the method as described above is used, a void (cavity) can be generated inside the bonding layer. This void may expand during a subsequent reflow step or cause separation or short-circuit. Especially when the surface on which the device comes into contact with the bonding layer is uneven, generation of a void becomes significant. There is concern that the generation of such a void may affect the formability and the connection reliability of the conductive via or the insulation performance. Especially in the case of a substrate with an embedded active device having a plurality of electrodes, voids cannot be usually removed by performing a void deaeration step. Since a wiring pattern is typically formed on the substrate surface at a position corresponding to a position between the electrodes, a void generated between these electrodes may cause short-circuit or migration between the electrode and the wiring pattern.